The present invention relates to a negative resistance device using an insulated gate field effect transistor (IGFET).
One of the known negative resistance devices is shown in FIG. 1 and is disclosed in an article "Semiconductor Transistor Study Material SSD, 72-41" published on 1972 by Tsushin Gakkai (the Japan Communication Society). Transistors Q1 and Q2 shown in FIG. 1 are each a metal oxide semiconductor field effect transistor (referred to as a MOS transistor) of the depletion type. Those transistors Q1 and Q2 are also of n- and p-channel types, being combined in a complementary MOS (C-MOS) fashion. Those transistors thus combined are conductive when the potential Vin at the input terminal Tin is low. As the potential Vin rises, the potential at the connection point A between the sources of the transistors Q1 and Q2 rises and the gate bias voltage of the transistor Q1 increases negatively. Accordingly, the channel conductance of the transistor Q1 decreases substantially exponentially and hence the drain current of the transistor Q1 decreases to render the transistor Q1 non-conductive. On the other hand, the gate bias of the transistor Q2 increases positively to render the transistor Q2 non-conductive. In this way, the circuit shown in FIG. 1 exhibits a negative resistance characteristic that, when the potential Vin is low, it is conductive but, when high, it is non-conductive.
The negative resistance device mentioned above utilizes the fact that the drain current depends on the gate bias and the operating current (drain current) is on the order of .mu.A to mA.
When the negative resistance device is applied to IC memories, for example, it is highly desirable to reduce the operating current. Further, in order to prevent punch-through, latch-up and the like, the drain areas of the transistors Q1 and Q2 must be widely separated each other with respect to the boundary between the semiconductor substrate and the p-well in the substrate, the boundary being interposed between both transistors. The wide separation between the drains hinders the improvement of the integration density when the circuit is fabricated by the IC technology.